In the semiconductor industry, there has recently been a high-level of activity using strained Si-based heterostructures to achieve high carrier mobility structures for CMOS applications. Traditionally, to boost performance of NFET and PFET devices, the prior art method to implement this has been to grow strained Si layers on thick (on the order of from about 1 to about 5 micrometers) relaxed SiGe buffer layers.
Despite the high channel electron mobilities reported for prior art heterostructures, the use of thick SiGe buffer layers has several noticeable disadvantages associated therewith. First, thick SiGe buffer layers are not typically easy to integrate with existing Si-based CMOS technology. Second, the defect densities, including threading dislocations (TDs) and misfit dislocations, are from about 106 to about 108 defects/cm2 which are still too high for realistic VLSI (very large scale integration) applications. Thirdly, the nature of the prior art structure precludes selective growth of the SiGe buffer layer so that circuits employing devices with strained Si, unstrained Si and SiGe materials are difficult, and in some instances, nearly impossible to integrate.
In order to produce relaxed SiGe material on a Si substrate, prior art methods typically grow a uniform, graded or stepped SiGe layer to beyond the metastable critical thickness (i.e., the thickness beyond which dislocations form to relieve stress) and allow misfit dislocations to form, with the associated threading dislocations, through the SiGe buffer layer. Various buffer structures have been used in an attempt to increase the length of the misfit dislocation section in the structures and thereby to decrease the TD density.
When a typical prior art metastable strained SiGe layer is annealed at a sufficiently high temperature, misfit dislocations will form and grow thereby relieving the total strain on the film. In other words, the initial elastic strain of the film is relieved by the onset of plastic deformation of the crystal lattice. For the case of prior art metastable strained SiGe grown on silicon-on-insulator (SOI) substrates, experiments have shown that under most annealing/oxidation conditions, the formation of misfit dislocations occurs early in the annealing history for temperatures greater than ˜700° C. Many of these defects are then either consumed or annihilated during the high-temperature annealing of the structure, however, the surface topography of the original misfit array persists during oxidation. Furthermore, SGOI substrate materials fabricated by thermal diffusion do not completely relax the SiGe alloy layer. Instead, the final SiGe lattice expands only to some fraction of the equilibrium value.
In addition to growing thick SiGe buffer layers atop an SOI substrate and then relaxing the SiGe layer by annealing/oxidation, it is also known to form SiGe-on-insulator substrates by wafer bonding and/or by oxygen implantation. Although these prior art processes are capable of forming relaxed SiGe-on-insulator substrates, they require additional processing steps, particularly in the case of wafer bonding, and/or add extra cost to the fabrication of SiGe-on-insulator substrates.
In view of the above drawbacks with the prior art, there is a need for providing a simple, yet low-cost method of forming high-quality, substantially relaxed SiGe-on-insulator substrates which can be used as a lattice mismatched template for forming a strained Si layer thereon.